Adding support to a new FPGA board on Chisel sample project using FuseSoc

This post originated from a live-tweed. The thread can be seen at https://twitter.com/carlosedp/status/1382057618114494465.

I'll show here how to add support for a new board, the Digilent ArtyA7, a very popular FPGA board based on Xilinx Artix7, to my Chisel ChiselBlinky project including FuseSoc support.

Chisel is an HDL (Hardware Design Language) based on Scala that provides more abstractions and the power of a fully-featured language to generate hardware.

FuseSoc is a package manager and generator for FPGA designs. With FuseSoc you can instantiate modules and define how each design will be generated on a multitude of FPGA backends. Usually each FPGA vendor has it's own tool (called EDA) and have a very particular way of defining how things are done. FuseSoc abstracts most of this for you.

ChiselBlinky is a demo project I made as a learning exercise and a template for new Chisel projects. It's just a simple module that blinks three LED s based on a clock and has a reset button.

Disclaimer: I’ve never used Xilinx FPGAs and Vivado before and will discover how to use it as I go.

Requirements

Blinky expects five IO pins, a clock input, a reset button and three leds.
The clock is fed into a PLL to generate a 25Mhz output. The PLL is a blackbox that wraps a vendor PLL IP Verilog source added to the resources folder. I made it in a way that the file can be dynamically defined based on a parameter.

The Toplevel module

Here is the PLL blackbox module:

import chisel3._
import chisel3.util._
class PLL0(board: String) extends BlackBox with HasBlackBoxResource {
  val io = IO(new Bundle() {
    val clki = Input(Clock())
    val clko = Output(Clock());
    val lock = Output(Clock())
  })
addResource("/pll_" + board + ".v")
}

ChiselBlink expects the PLL Verilog to live in the src/main/resources dir named as “pll_boardname.v”. We will get to it soon.